@inproceedings{ECC:ECP,
 author = {Schechter, S. and others},
 title = {Use ECP, not ECC, for hard failures in resistive memories},
 booktitle = {Proceedings of the 37th annual international symposium on Computer architecture},
 series = {ISCA 2010},
 year = {2010},
 pages = {141--152},
 numpages = {12},
 keywords = {error correction, hard failures, memory, phase change memory, resistive memories},
}

@inproceedings{ECC:FreeP,
 author = {Yoon, D.H. and others},
 title = {FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors},
 booktitle = {Int. Symp. on High-Performance Computer Architecture Conference},
 series = {HPCA 2011},
 year = {2011},
 keywords = {error correction, hard failures, memory, phase change memory, resistive memories},
}



@INPROCEEDINGS{ECC:PACT,
author={Wangyuan Zhang and Tao Li},
booktitle={Parallel Architectures and Compilation Techniques, 2009. PACT '09. 18th International Conference on}, title={Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures},
year={2009},
month=sept.,
volume={},
number={},
pages={101 -112},
keywords={3D die-stacking;3D integration technology;DRAM;ECC codes;OS-level paging;PRAM;alleviating memory latency;bandwidth constraints;charge leakage;durable memory architectures;endurance optimization;error-correcting capability;heat-driven programming mechanisms;microprocessor;on-chip temperature;phase-change random access memory;power density;through silicon vias;wire-delay;DRAM chips;concurrency theory;error correction codes;microassembling;optimisation;phase change memories;},
doi={10.1109/PACT.2009.30},
ISSN={1089-795X},}

@INPROCEEDINGS{ECC:BCH,
author={Strukov, D.},
booktitle={Signals, Systems and Computers, 2006. ACSSC '06. Fortieth Asilomar Conference on}, title={The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories},
year={2006},
month=29 2006-nov. 1,
volume={},
number={},
pages={1183 -1187},
keywords={Hamming distance;binary bit-parallel BCH ECC decoders;error correcting capability;random access nanoelectronic memories;BCH codes;Hamming codes;binary codes;decoding;error correction codes;nanoelectronics;random-access storage;},
doi={10.1109/ACSSC.2006.354942},
ISSN={1058-6393},}

@ARTICLE{cpu:Opteron,
author={Keltcher, C.N. and McGrath, K.J. and Ahmed, A. and Conway, P.},
journal={Micro, IEEE}, title={{The AMD Opteron processor for multiprocessor servers}},
year={2003},
month=march-april,
volume={23},
number={2},
pages={ 66 - 76},
keywords={AMD Opteron processor; DDR memory controller; X86-64 architecture; backwards compatibility; hypertransport links; multiprocessor servers; server-class performance; microprocessor chips; parallel architectures;},
doi={10.1109/MM.2003.1196116},
ISSN={0272-1732},}

@techreport{cpu:AMD,
author={Kim, J.},
title={White Paper: The {AMD Athlon MP processor with 512 KB L2 cache}},
year={2003},
ISSN={0272-1732},}
